OPEN TO CO-OP / INTERNSHIPS

Armaan Bains

Embedded Systems & Systems Software Engineer: firmware, digital hardware, and low-level software. ECE student at the University of Toronto, building high-performance systems from bare-metal C++ up to custom RTL and robotics.

Armaan Bains

About

I'm an Electrical and Computer Engineering student at the University of Toronto (BASc + PEY Co-op), focused on embedded firmware, digital hardware, and systems software development. Most of my work lives in C++ close to the metal, whether that's architecting large-scale GIS routing engines and low-latency algorithms, driving PWM peripherals, or implementing the real-time kinematics that keep a robotic arm on target.

I like projects that force me to understand a system end to end: from a transistor-level PCB trace and bare-metal firmware, up to the algorithms, data structures, and vision models running on top.

Skills

LANGUAGES
C++, C, Python, Verilog / SystemVerilog / RTL, RISC-V Assembly
HARDWARE
PCB Design (KiCad), I2C / PWM, Altium Viewer, Cadence, Fusion 360
TOOLING
Quartus Prime, Xilinx Vivado, SignalTap, ModelSim, GTK, GDB, Git / Perforce
DOMAINS
Firmware / hardware debugging, pre-silicon emulation, computer vision (OpenCV, YOLOv8), Linux development
TEAM
Technical communication, cross-functional collaboration, project management, team leadership

Experience

May 2025 to
Sep 2025

Research Intern

Intelligent Sensory Microsystems Lab (ISML), University of Toronto

  • Reverse-engineered top-level Verilog RTL across 5+ major Time-of-Flight sensor source files, mapping FSMs, ADC readout control signals, and pixel-bucket timing diagrams into system breakdowns.
  • Engineered Python control scripts to drive microcontroller GPIO pins on camera-ToF PCBs, dynamically triggering Verilog timing state transitions for live parameter testing by lab researchers.
  • Performed waveform-level signal analysis and PCB signal tracing to debug timing issues and firmware/hardware mismatches across 3 PCB revisions.
  • Documented verification findings and presented architectural breakdowns across 16+ peer design reviews.
May 2024 to
Sep 2024

Produce & Overnight Stocking Associate

Costco Wholesale

  • Managed high-volume inventory flow and overnight restocking across departments to prepare the warehouse for daily operations.
  • Assisted members with product inquiries, location guidance, and service needs in a fast-paced retail environment.

Projects

Autonomous object tracking robotic arm prototype
Autonomous Object Tracking Robotic Arm
2026

C++ · Python · OpenCV · ESP32 · YOLOv8 · Fusion 360

  • Built a real-time embedded firmware stack on an ESP32 driving a 5-channel servo array via 12-bit hardware PWM at 50Hz, utilizing native PWM drivers without external convenience libraries.
  • Wrote a custom 3D geometric Inverse Kinematics engine in C++ to convert Cartesian target vectors into joint duty cycles in real time.
  • Implemented an automated wrist self-leveling loop to counter-rotate the end-effector and hold a stable posture through fast movements.
  • Built a vision pipeline with a custom-trained YOLOv8 model to map pixel coordinates to physical workbench coordinates for closed-loop pick-and-place.
  • Designed a parallel-tracking gripper with passive compliance, and every mechanical component of the arm, in Fusion 360.
FluxGrip AI real-time embedded performance analytics interface tracking workout reps
FluxGrip: Workout Set & Rep Tracker
Jul 2026

C++ · ESP32 · TinyML · KiCad · I2C

  • Wrote a bare-metal C++ I2C driver for an MPU-6050 IMU, parsing raw 6-axis accelerometer and gyroscope data.
  • Built a spatial orientation and kinematics engine using Mahony sensor fusion and quaternion math, feeding an on-device Edge Impulse TinyML model across 10+ exercise classes.
  • Engineered real-time peak-detection algorithms to identify rep boundaries and segment eccentric and concentric phases.
  • Designed a custom two-layer PCB in KiCad integrating the ESP32 and IMU into a wearable form factor.
FPGA neural network accelerator hardware layout and waveforms
Neural Network Hardware Accelerator (MNIST)
Aug 2026

SystemVerilog · PyTorch · ModelSim · Quartus · DE1-SoC

  • Architected an INT8 deep learning accelerator on a Cyclone V FPGA (DE1-SoC) for MNIST inference, engineering a custom post-training quantization pipeline with 20-bit accumulator-scaled biases to resolve input background DC offsets.
  • Designed an RTL datapath featuring an 8-bit signed MAC engine, a 27-bit accumulator, and fixed-point hardware requantization (∗1462⋙20) with saturation clamping alongside custom ReLU and ArgMax modules.
  • Implemented a multi-state control FSM executing full inference in 31,610 clock cycles (632.2 μs latency at 50 MHz), achieving over 1,580 classifications/sec verified on-chip via Signal Tap Logic Analyzer.
RISC-V CPU Emulator & Assembler
Mar 2026

C++ · RISC-V Assembly · FTXUI · Linux

  • Built a cycle-accurate CPU emulator in C++ decoding and executing the RV32I base instruction set, with a 32-entry register file and a 1MB simulated RAM system bus.
  • Developed an integrated single-pass assembler to compile human-readable assembly into 32-bit machine code in real time.
  • Built an interactive terminal debugger with FTXUI featuring live register visualization, aligned memory hex dumps, and single-step execution.
GIS navigation application showing a routable street map of Toronto alongside the control panel with search, zoom, and category filters
GIS Navigation Application
2025

C++ · GTK · GDB · Linux

  • Architected high-performance spatial data structures using hash maps and sets to index OpenStreetMap entities, enabling low-latency intersection lookups and street topology queries.
  • Implemented geographic distance algorithms using spherical to Cartesian equirectangular projections and engineered set-intersection routines to identify multi-street junctions.
  • Built an interactive GTK search interface featuring real-time autocomplete via case-insensitive prefix-matching algorithms and dual-point intersection highlighting.

Education

BASc, Electrical and Computer Engineering + PEY Co-op

University of Toronto

Relevant coursework: Computer Organization, Digital Systems, Electronics, Circuit Analysis, Signals & Systems.

Awards

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1st Place, UTEK Junior Design Competition: OEC Provincial Finalist. Engineered a winning design prototype under strict time and material constraints, selected to represent U of T at the Ontario Engineering Competition.